The present invention relates to a MOS memory device which includes a memory circuit composed of insulated gate type field effect transistors (MOSFET's) and a driver for driving the memory circuit, and more specifically to a memory device (N-MOS memory) having a memory circuit composed of N-channel insulated gate type field effect transistors (NMOSFET's) and a driver which is compensated against the fluctuation in power-supply voltage.
Conventional N-MOS memories consist, as shown in FIG. 1, of a memory circuit 100, and drivers 300 to 330 for driving the memory circuit. The memory circuit 100 has a plurality of memory chips 200 which are served with chip select signals CS, row address strobe signals RAS, column address strobe signals CAS, and writing signals WRITE, which are respectively supplied from the drivers 300 to 330 through common signal lines. To read the memory, address signals A.sub.1 to A.sub.6 are fed to each of the chips through common signal lines, whereby a data DATA OUT is read out from each of the chips. To write the memory, a data DATA IN is supplied to each of the chips 200 together with the address signals A.sub.1 to A.sub.6. A voltage V.sub.CC of a positive polarity, a voltage V.sub.EE of a negative polarity and a ground voltage V.sub.SS are supplied from predetermined power-supply terminals to the memory circuit 100; these voltages are supplied to each of the chips 200 via common power-supply lines (not shown).
Referring to FIG. 2, the memory circuit 100 consists of a clock signal generator circuit 6, which, upon receipt of the row address strobe signal RAS, produces a row enabling clock signal for introducing row address information, a clock signal generator circuit 8 which produces a column enabling clock signal for introducing column address information upon receipt of the row address strobe signal RAS and column address strobe signal CAS through a gate circuit 7, a control circuit 9 which, upon receipt of clock signals from the clock signal generator circuits 6 and 8, controls an address buffer circuit 13 and an address decoder circuit 14 which enables 54 row lines and 32 column select lines, a buffer circuit 10 which receives the chip select signals CS, a gate circuit 12 which, upon receipt of output signals from the clock signal generator circuit 8 and the buffer circuit 10, produces a column enabling signal to the address decoder circuit 14 and an enabling signal to a data output buffer circuit 17 which is reset by the CAS signal and produces a data DATA OUT when it is enabled, a gate circuit 11 which controls the operation of a write clock signal generator circuit 15 upon receipt of the write control signal WRITE and an output signal from the gate circuit 7, a data input buffer circuit 16 which receives a data DATA IN in response to an enabling signal provided by the write clock signal generator circuit 15, memory arrays 18 and 18', a pre-amplifier group 19, and an input/output data line selector circuit 20.
Signals CS, RAS, CAS, WRITE and A.sub.1 to A.sub.6 are received by the memory circuit 100 through inverters 5. When the memory circuit 100 is not to be driven, the drive signals CS, RAS, CAS are in a high level, and when the memory circuit 100 is to be driven, the drive signals are in a low level. The reason is because, the operation of the memory circuit 100 can be quickly raised when the drive signals of such levels are used. Below is mentioned with regard to this point.
With reference to FIG. 3, the inverter circuit 5 consists of MOSFET's Q.sub.24 to Q.sub.28 and a capacitor C.sub.1. MOSFET's Q.sub.24 to Q.sub.26 and capacitor C.sub.1 constitute an inverter circuit, and MOSFET's Q.sub.27 and Q.sub.28 constitute a push-pull output circuit.
FIG. 4 illustrates waveforms A, B and C of an input signal fed to the inverter circuit, a source voltage of the MOSFET Q.sub.25, and a gate voltage of the MOSFET Q.sub.25. When the input signal A is of the high level, the MOSFET's Q.sub.26 and Q.sub.28 are rendered conductive, so that source voltage B of the MOSFET Q.sub.25 as well as the source voltage of the MOSFET Q.sub.27 acquire the low level which is approximately equal to the ground potential. In this case, the capacitor C.sub.1 is electrically charged to acquire a value V.sub.CC -V.sub.th which is equal to the power-supply voltage V.sub.CC minus a threshold voltage V.sub.th of the MOSFET Q.sub.24 which is diode-connected.
When the input signal A is changed from the high level to the low level, the MOSFET's Q.sub.26 and Q.sub.28 are rendered non-conductive, so that source voltage B of the MOSFET Q.sub.25 as well as the source voltage of the MOSFET Q.sub.27 starts to rise. Here, since the capacitor C.sub.1 has been electrically charged beforehand to a value close to V.sub.CC -V.sub.th, the gate voltage of MOSFET Q.sub.25 becomes sufficiently great. As a result, the resistance of MOSFET Q.sub.25 while it is conductive is sufficiently reduced. As the resistance of MOSFET Q.sub.25 while it is conductive is sufficiently reduced, a stray capacity C.sub.2 between the source of MOSFET Q.sub.25 and the ground is quickly charged, so that a source voltage B of MOSFET Q.sub.25 is raised at a high speed. Owing to the bootstrap effect of the capacitor C.sub.1, the gate voltage C of MOSFET Q.sub.25 rapidly rises responsive to the rise in the source voltage. As the gate voltage C becomes greater than the power-supply voltage V.sub.CC, the source voltage B of MOSFET Q.sub.25 rises to a value close to the power-supply voltage V.sub.CC regardless of the threshold voltage possessed by the MOSFET Q.sub.25. The output signal supplied from the source of MOSFET Q.sub.27 also rises quickly with the rise in the source voltage B of MOSFET Q.sub.25. Accordingly, various elements in the memory circuit 100 rise quickly responsive to the output of the inverter circuit 5. However, if a signal which rises from the low level to the high level is used to drive the memory circuit, the rise of the memory circuit 100 will become sluggish. In order for the memory circuit 100 to be driven by a signal which rises from the low level to the high level, the memory circuit must be provided with two stages of inverter circuits. Therefore, the operation speed of the memory circuit becomes sluggish as compared with the case when one stage of inverter circuit is employed. Because of the above-mentioned reasons, with the conventional memory devices, the memory circuit 100 is so constructed as to receive a driving signal which acquires the high level during the period of non-operation and the low level during the period of operation such that the operation speed can be increased, and the drivers are so constructed as to produce such driving signals.
With the conventional memory devices, however, if the circuits of power supplies V.sub.CC and V.sub.EE are closed in an incorrect sequence, overcurrents will flow into the drivers 300 to 330.
For example, when the predetermined voltage V.sub.CC of positive polarity is supplied to the memory device without supplying the voltage V.sub.EE of negative polarity, the drivers 300 to 330 will permit excess of currents to flow therethrough so that driving signals of the high level are produced. When such a state is sustained, however, transistors for producing driving signals in the drivers will be broken down. In order to preclude such inconvenience, the conventional class-1 memory devices are equipped with a breaker (not shown) in the power-supply circuit to interrupt the power supply when overcurrents start to flow, and the conventional class-2 memory devices are equipped with a sequencer (not shown) to define the order of closing the power-supply circuits. With the former memory devices, however, the circuits of power supplies must be closed again after they have been interrupted by the breaker. With the latter memory devices employing a sequencer, on the other hand, the manufacturing costs are increased.
Further, the phenomenon of overcurrents which flow when the power-supply voltages are not proper, takes place when the power-supply voltages are varied after the power supplies have been connected.
The power-supply voltage fluctuates even when a constant voltage is supplied to the memory device from an external unit. For example, when the drivers 300 to 330 are constructed in the form of a monolithic device by the technique of integrated circuit, the power-supply voltages practically supplied to each of the drivers undergo fluctuation depending upon the operation conditions of various circuits included in the monolithic device.
With the conventional class-1 memory devices, if the fluctuation in power-supply voltages exceeds a limit value, the power supplies are interrupted even when the fluctuation develops temperarily, resulting in the interruption of operation of the memory devices. Furthermore, with the conventional class-2 memory devices, it is difficult to prevent the drivers from being broken down by overcurrents. According to the conventional memory devices, therefore, it is necessary to employ a sequencer for assuring the order of closing the power-supply circuits as well as a breaker for preventing the drivers from being broken down after the power supplies have been connected. This means that increased costs are required for manufacturing the memory devices.